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fds8978 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation fds8978 rev. b1 1 g2 s2 g1 s1 d2 d2 d1 d1 d1 d2 s1 g1 s2 g2 d1 d2 1 2 3 4 8 7 6 5 q1 q2 pin 1 so-8 fds8978 n-channel powertrench ? mosfet 30v, 7.5a, 18m ? features ? r ds(on) = 18m ? , v gs = 10v, i d = 7.5a ? r ds(on) = 21m ? , v gs = 4.5v, i d = 6.9a ? high performance trench technology for extremely low r ds(on) ? low gate charge ? high power and current handling capability ? 100% rg tested ? rohs compliant general description this n-channel mosfet has be en designed specifically to improve the overall efficienc y of dc/dc converters using either synchronous or conventional switching pwm controllers. it has been optimized for low gate charge, low r ds(on) and fast switching speed. applications ? dc/dc converters mosfet maximum ratings t a = 25c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v dss drain to source voltage 30 v v gs gate to source voltage 20 v i d drain current 7.5 a continuous (t a = 25 o c, v gs = 10v, r ja = 50 o c/w) continuous (t a = 25 o c, v gs = 4.5v, r ja = 50 o c/w) 6.9 a pulsed 49 a e as single pulse avalanche energy (note 1) 57 mj p d power dissipation 1.6 w derate above 25 o c13mw/ o c t j , t stg operating and storage temperature -55 to 150 o c r jc thermal resistance, junction to case (note 2) 40 o c/w r ja thermal resistance, junction to ambient (note 2a) 78 o c/w r ja thermal resistance, junction to ambient (note 2c) 135 o c/w device marking device package reel size tape width quantity fds8978 fds8978 so-8 330mm 12mm 2500 units january 2011 www.fairchildsemi.com
fds8978 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation fds8978 rev. b1 www.fairchildsemi.com 2 electrical characteristics t j = 25c unless otherwise noted symbol parameter test conditions min typ max units off characteristics b vdss drain to source breakdown voltage i d = 250 p a, v gs = 0v 30 - - v i dss zero gate voltage drain current v ds = 24v - - 1 p a v gs = 0v t j = 150 o c - - 250 i gss gate to source leakage current v gs = 20v - - 100 na on characteristics v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 p a 1.2 - 2.5 v r ds(on) drain to source on resistance i d = 7.5a, v gs = 10v - 14 18 m : i d = 6.9a, v gs = 4.5v - 17 21 i d = 7.5a, v gs = 10v, t j = 150 o c - 22 29 dynamic characteristics c iss input capacitance v ds = 15v, v gs = 0v, f = 1mhz - 907 1270 pf c oss output capacitance - 191 - pf c rss reverse transfer capacitance - 112 - pf r g gate resistance v gs = 0.5v, f = 1mhz - 1.2 4.0 : q g(tot) total gate charge at 10v v gs = 0v to 10v v dd = 15v i d = 7.5a - 17 26 nc q g(5) total gate charge at 5v v gs = 0v to 5v - 9 14 nc q gs gate to source gate charge - 2.3 - nc q gs2 gate charge threshold to plateau - 1.5 - nc q gd gate to drain ?miller? charge - 3.3 - nc switching characteristics (v gs = 10v) t on turn-on time v dd = 15v, i d = 7.5a v gs = 10v, r gs = 16 : - 44 66 ns t d(on) turn-on delay time - 7 10.5 ns t r rise time - 37 55.5 ns t d(off) turn-off delay time - 48 72 ns t f fall time - 24 36 ns t off turn-off time - 72 108 ns drain-source diode characteristics v sd source to drain diode voltage i sd = 7.5a - - 1.25 v i sd = 2.1a - - 1.0 v t rr reverse recovery time i sd = 7.5a, di sd /dt = 100a/ p s - 19 25 ns q rr reverse recovered charge i sd = 7.5a, di sd /dt = 100a/ p s - 10 13 nc notes: 1: starting t j = 25c, l = 1mh, i as = 7.5a, v dd = 30v, v gs = 10v. 2: r t ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the s older mounting surface of the drain pins. r t jc is guaranteed by design while r t ja is determined by the user?s board design. a) 78c/w when mounted on a 0.5 in 2 pad of 2 oz copper. b) 125c/w when mounted on a 0.02 in 2 pad of 2 oz copper. c) 135c/w when mounted on a minimun pad.
fds8978 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation fds8978 rev. b1 www.fairchildsemi.com 3 typical characteristics t j = 25c unless otherwise noted figure 1. t a , ambient temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 normalized power dissipation vs ambient temperature figure 2. 25 50 75 100 125 150 0 1 2 3 4 5 6 7 8 r t ja = 78 o c/w v gs = 4.5v v gs = 10v i d , drain current (a) t a , ambient temperature ( o c ) maximum continuous drain current vs ambient temperature figure 3. 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 0.001 0.01 0.1 1 single pulse r t ja = 135 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (s) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 normalized maximum transient thermal impedance figure 4. 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 1 10 100 1000 p (pk) , peak transient power (w) v gs = 10v single pulse r t ja = 135 o c/w t a = 25 o c t, pulse width (s) 0.5 single pulse maximum power dissipation
fds8978 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation fds8978 rev. b1 www.fairchildsemi.com 4 note: refer to fairchild application notes an7514 and an7515 figure 5. 1 10 100 0.01 0.1 1 10 100 i as , avalanche current (a) t av , time in avalanche (ms) starting t j = 25 o c starting t j = 150 o c t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r z 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] unclamped inductive switching capability figure 6. 12345 0 10 20 30 40 50 v ds = 5v pulse duration = 80 p s duty cycle = 0.5%max t j = -55 o c t j = 25 o c t j = 150 o c i d , drain current (a) v gs , gate to source voltage (v) transfer characteristics figure 7. saturation characteristics 0.0 0.2 0.4 0.6 0.8 1.0 0 10 20 30 40 50 v gs = 4.5v v gs = 5v v gs = 3.5v pulse duration = 80 p s duty cycle = 0.5%max v gs = 3v v gs = 10v i d , drain current (a) v ds , drain to source voltage (v) figure 8. 0 10 20 30 40 50 246810 v gs , gate to source voltage (v) i d = 10.2a r ds(on) , drain to source on resistance (m w ) pulse duration = 80 p s duty cycle = 0.5% max i d = 1a drain to source on resistance vs gate voltage and drain current figure 9. 0.8 1.0 1.2 1.4 1.6 normalized drain to source t j , junction temperature ( o c) on resistance v gs = 10v, i d = 10.2a pulse duration = 80 p s duty cycle = 0.5% max -80 -40 0 40 80 120 160 normalized drain to source on resistance vs junction temperature figure 10. normalized gate t j , junction temperature ( o c) v gs = v ds , i d = 250 p a threshold voltage 0.6 0.8 1.0 1.2 -80 -40 0 40 80 120 160 normalized gate threshold voltage vs junction temperature typical characteristics t j = 25c unless otherwise noted
fds8978 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation fds8978 rev. b1 www.fairchildsemi.com 5 figure 11. 0.90 0.95 1.00 1.05 1.10 t j , junction temperature ( o c) normalized drain to source i d = 250 p a breakdown voltage -80 -40 0 40 80 120 160 normalized drain to source breakdown voltage vs junction temperature figure 12. 10 1000 0.1 1 10 2000 30 c, capacitance (pf) v gs = 0v, f = 1mhz c iss = c gs + c gd c oss # c ds + c gd c rss = c gd v ds , drain to source voltage (v) capacitance vs drain to source voltage figure 13. 0 2 4 6 8 10 v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 15v i d = 7.5a i d = 1a waveforms in descending order: 0369121518 gate charge wavefo rms for constant gate currents figure 14. forward bias safe operating area 0.01 0.1 1 10 100 0.01 0.1 1 10 dc 10s 1s 100ms 10ms 1ms 100us i d , drain current (a) v ds , drain to source voltage (v) 60 this area is limited by r ds(on) single pulse t j = max rated r t ja = 125 o c/w t a = 25 o c typical characteristics t j = 25c unless otherwise noted
test circuits and waveforms figure 15. t p v gs 0.01 : l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v unclamped energy test circuit figure 16. v dd v ds bv dss t p i as t av 0 unclamped energy waveforms figure 17. v gs + - v ds v dd dut i g(ref) l gate charge test circuit figure 18. v dd q g(th) v gs = 1v q gs2 q g(tot) v gs = 10v v ds v gs i g(ref) 0 0 q gs q gd q g(5) v gs = 5v gate charge waveforms figure 19. v gs r l r gs dut + - v dd v ds v gs switching time test circuit figure 20. t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 switching time waveforms fds8978 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation fds8978 rev. b1 www.fairchildsemi.com 6
fds8978 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation fds8978 rev. b1 www.fairchildsemi.com 7 thermal resistance vs. mounting pad area the maximum rated junction temperature, t jm , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, p dm , in an application. therefore the application?s ambient temperature, t a ( o c), and thermal resistance r t ja ( o c/w) must be reviewed to ensure that t jm is never exceeded. equation 1 mathematically represents the relationship and serves as the basis for establ ishing the rating of the part. (eq. 1) p dm t jm t a ? r t ja ------------------------------ - = in using surface mount devices such as the so8 package, the environment in which it is applied will have a significant influence on the part?s current and maximum power dissipation ratings. prec ise determination of p dm is complex and influenced by many factors: 1. mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. the number of copper layers and the thickness of the board. 3. th e use of external heat sinks. 4. the use of thermal vias. 5. air flow and board orientation. 6. for non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. fairchild provides thermal information to assist the design - er?s preliminary application eval uation. figure 21 defines the r t ja for the device as a function of the top copper (compo - nent side) area. this is for a horizontally positioned fr-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. this graph provides the necessary in - formation for calculation of the steady state junction temper - ature or power dissipation. pulse applications can be evaluated using the fairchild device spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. thermal resistances corresponding to other copper areas can be obtained from figure 21 or by calculation using equation 2. the area, in square inches is the top copper area including the gate and source pads. (eq. 2) r t ja 64 26 0.23 area + ------------------------------- + = the transient thermal impedance (z t ja ) is also effected by varied top copper board area. figure 22 shows the effect of copper pad area on single pulse transient thermal imped - ance. each trace represents a copper pad area in square inches corresponding to the descending list in the graph. spice and saber thermal models are provided for each of the listed pad areas. copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. for pulse widths less than 100ms the transient thermal impedance is determined by the die and package. therefore, ctherm1 through ctherm5 and rtherm1 through rtherm5 remain constant for each of the thermal models. a listing of the model component values is available in table 1. 100 150 200 0.001 0.01 0.1 1 10 50 figure 21. thermal resistance vs mounting pad area r t ja = 64 + 26/(0.23+area) r t ja ( o c/w) area, top copper area (in 2 ) 0 30 60 90 120 150 10 -1 10 0 10 1 10 2 10 3 figure 22. thermal impedance vs mounting pad area t, rectangular pulse duration (s) z t ja , thermal copper board area - descending order 0.04 in 2 0.28 in 2 0.52 in 2 0.76 in 2 1.00 in 2 impedance ( o c/w)
fds8978 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation fds8978 rev. b1 www.fairchildsemi.com 8 pspice electrical model .subckt fds8978 2 1 3 *february 2005 ca 12 8 7.8e-10 cb 15 14 7.8e-10 cin 6 8 .78e-9 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 32.9 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 lgate 1 9 5.29e-9 ldrain 2 5 1.0e-9 lsource 3 7 0.18e-9 rlgate 1 9 52.9 rldrain 2 5 10 rlsource 3 7 1.8 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rd rainmod 1.6e-3 rgate 9 20 2.3 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 8.9e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5, 51)))*(pwr(v(5,51) /(1e-6*170),5))} .model dbodymod d (is=2.0e-12 ikf=10 n=1.01 rs=7.0e-3 trs1=8e-4 trs2=2e-7 + cjo=3.5e-10 m=0.55 tt=7e-11 xti=2) .model dbreakmod d (rs=0.2 trs1=1e-3 trs2=-8.9e-6) .model dplcapmod d (cjo=3.8e-10 is=1e-30 n=10 m=0.45) .model mstromod nmos (vto=2.36 kp =150 is=1e-30 n=10 tox=1 l=1u w=1u) .model mmedmod nmos (vto=1.95 kp=5.0 is =1e-30 n=10 tox=1 l=1u w=1u rg=2.3) .model mweakmod nmos (vto=1.57 kp=0.02 is=1e-30 n=10 tox=1 l=1u w=1u rg=23 rs=0.1) .model rbreakmod res (tc1=8.3e-4 tc2=-8e-7) .model rdrainmod res (tc1=15e-3 tc2=0.1e-5) .model rslcmod res (tc1=1e-4 tc2=1e-6) .model rsourcemod res (tc1=1e-3 tc2=3e-6) .model rvtempmod res (tc1=-1.8e-3 tc2=2e-7) .model rvthresmod res (tc1=-2.0e-3 tc2=-6e-6) model s1amod vswitch (ron=1e- 5 roff=0.1 von=-4 voff=-3.5) .model s1bmod vswitch (ron=1e- 5 roff=0.1 von=-3.5 voff=-4) .model s2amod vswitch (ron=1e- 5 roff=0.1 von=-1.5 voff=-1.0) .model s2bmod vswitch (ron=1e-5 roff=0. 1 von=-1.0 voff=-1.5).endsnote: for fu rther discussion of the pspice mod - el, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6
fds8978 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation fds8978 rev. b1 www.fairchildsemi.com 9 saber electrical model rev february 2005 template fds8978 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2.0e-12,ikf =10,nl=1.01,rs=7.0e-3,trs1 =8e-4,trs2=2e-7,cjo=3.5e-1 0,m=0.55,tt=7e-11,xti=2) dp..model dbreakmod = (rs=0.2,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=3.8 e-10,isl=10e-30,nl=10,m=0.45) m..model mstrongmod = (type=_n,vto=2.36,kp=150,is=1e-30, tox=1) m..model mmedmod = (type=_n,vto=1.95,kp=5.0,is=1e-30, tox=1) m..model mweakmod = (typ e=_n,vto=1.57,kp= 0.02,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e -5,roff=0.1,von= -4,voff=-3.5) sw_vcsp..model s1bmod = (ron=1e -5,roff=0.1,von= -3.5,voff=-4) sw_vcsp..model s2amod = (ron=1e-5 ,roff=0.1, von=-1.5,voff=-1.0) sw_vcsp..model s2bmod = (ron=1e-5 ,roff=0.1, von=-1.0,voff=-1.5) c.ca n12 n8 = 7.8e-10 c.cb n15 n14 = 7.8e-10 c.cin n6 n8 = .78e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 32.9 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 5.29e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 0.18e-9 res.rlgate n1 n9 = 52.9 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 1.8 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-8e-7 res.rdrain n50 n16 = 1. 6e-3, tc1=15e-3,tc2=0.1e-5 res.rgate n9 n20 = 2.3 res.rslc1 n5 n51 = 1e-6, tc1=1e-4,tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 8. 9e-3, tc1=1e-3,tc2=3e-6 res.rvthres n22 n8 = 1, tc1=-2.0e-3,tc2=-6e-6 res.rvtemp n18 n19 = 1, tc1=-1.8e-3,tc2=2e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v( n5,n51))))*((abs(v(n5,n51)*1e6/170))** 5)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6
fds8978 dual n-channel powertrench ? mosfet ?2011 fairchild semiconductor corporation fds8978 rev. b1 www.fairchildsemi.com 10 spice thermal model rev february 2005 template fds8878 n2,n1,n3 copper area =1.0 in 2 ctherm1 th 8 2.0e-3 ctherm2 8 7 5.0e-3 ctherm3 7 6 1.0e-2 ctherm4 6 5 4.0e-2 ctherm5 5 4 9.0e-2 ctherm6 4 3 2e-1 ctherm7 3 2 1 ctherm8 2 tl 3 rtherm1 th 8 1e-1 rtherm2 8 7 5e-1 rtherm3 7 6 1 rtherm4 6 5 5 rtherm5 5 4 8 rtherm6 4 3 12 rtherm7 3 2 18 rtherm8 2 tl 25 saber thermal model copper area = 1.0 in 2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 =2.0e-3 ctherm.ctherm2 8 7 =5.0e-3 ctherm.ctherm3 7 6 =1.0e-2 ctherm.ctherm4 6 5 =4.0e-2 ctherm.ctherm5 5 4 =9.0e-2 ctherm.ctherm6 4 3 =2e-1 ctherm.ctherm7 3 2 1 ctherm.ctherm8 2 tl 3 rtherm.rtherm1 th 8 =1e-1 rtherm.rtherm2 8 7 =5e-1 rtherm.rtherm3 7 6 =1 rtherm.rtherm4 6 5 =5 rtherm.rtherm5 5 4 =8 rtherm.rtherm6 4 3 =12 rtherm.rtherm7 3 2 =18 rtherm.rtherm8 2 tl =25 } table 1. thermal models componant 0.04 in 2 0.28 in 2 0.52 in 2 0.76 in 2 1.0 in 2 ctherm6 1.2e-1 1.5e-1 2.0e-1 2.0e-1 2.0e-1 ctherm7 0.5 1.0 1.0 1.0 1.0 ctherm8 1.3 2.8 3.0 3.0 3.0 rtherm6 26 20 15 13 12 rtherm7 39 24 21 19 18 rtherm8 55 38.7 31.3 29.7 25 rtherm6 rtherm8 rtherm7 rtherm5 rtherm4 rtherm3 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 7 junction case 8 th rtherm2 rtherm1 ctherm7 ctherm8
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?2011 fairchild semiconductor corporation fds8978 rev. b1 www.fairchildsemi.com 11

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